A Comparison of Floating Point and Logarithmic Number Systems on FPGAs

A Comparison of Floating Point and Logarithmic Number Systems on FPGAs Michael Haselman Chair of the Supervisory Committee: Associate Professor Scott Hauck Electrical Engineering There have been many papers proposing the use of logarithmic numbers (LNS) as an alternative to floating point because of simpler multiplication, division and exponentiation computations [Lewis93, Wan99, Coleman99, Coleman00, Detrey03, Lee03, Tsoi04]. However, this advantage comes at the cost of complicated, inexact addition and subtraction, as well as the possible need to convert between the formats. In this work, we created a parameterized LNS library of computational units and compared them to existing floating point libraries. Specifically, we considered the area and latency of multiplication, division, addition and subtraction to determine when one format should be used over the other. We also characterized the tradeoffs when conversion is required for I/O compatibility.